The present disclosure relates to a reference frequency generation circuit which generates a reference clock, and more particularly, relates to oscillation control in the reference frequency generation circuit.
Conventionally, a clock generation circuit such as a PLL and a DLL generates a clock having a desired frequency based on a reference frequency. As examples of such circuits for generating a reference frequency, RC oscillators each including a resistor and a capacitor, and IC oscillators each including a current source and a capacitor have been known. Such oscillators (reference frequency generation circuits) can be largely divided into the single-type oscillators, such as the oscillators disclosed in, e.g., Japanese Patent Publication No. H09-107273, Japanese Patent Publication No. H09-312552, etc., and the differential-type oscillators, such as the oscillators disclosed in, e.g., Japanese Patent Publication No. H06-77781, Japanese Patent Publication No. H10-70440, etc.
FIG. 24A is a diagram illustrating a configuration of a conventional single-type reference frequency generation circuit disclosed in H09-107273. In this circuit, an oscillator circuit 81 charges/discharges a capacitor C to output an oscillation signal OSC. An oscillation control circuit 82 outputs a reference clock CK to control the charging/discharging operation of the oscillator circuit 81.
As shown in FIG. 24B, when a signal level of the oscillation signal OSC has reached a predetermined voltage VH, the reference clock CK transitions from the low level to the high level. Thus, the capacitor C is discharged, and the signal level of the oscillation signal OSC is reduced. After a predetermined time has elapsed, the reference clock CK transitions from the high level to the low level. Thus, the capacitor C is charged, and the signal level of the oscillation signal OSC is increased. In the above-described manner, the reference flock CK having a frequency corresponding to a time constant of the oscillator circuit 81 is generated.
FIG. 25A is a diagram illustrating a configuration of a conventional differential-type reference frequency generation circuit disclosed in Japanese Patent Publication No. H06-77781. In this circuit, an oscillator circuit 91 charges/discharges capacitors C1 and C2 to output oscillation signals OSC1 and OSC2. An oscillation control circuit 92 outputs reference clocks CK1 and CK2 to control the charging/discharging operation of the oscillator circuit 91.
As shown in FIG. 25B, when a signal level of the oscillation signal OSC1 has reached a threshold voltage VT1 of an inverter 901, the reference clock CK1 transitions from the low level to the high level, and the reference clock CK2 transitions from the high level to the low level. Thus, the capacitor C1 is discharged, and the signal level of the oscillation signal OSC1 is reduced, while the capacitor C2 is charged, and a signal level of the oscillation signal OSC2 is increased. Next, when the signal level of the oscillation signal OSC2 has reached a threshold voltage VT2 of an inverter 902, the reference clock CK1 transitions from the high level to the low level, and the reference clock CK2 transitions from the low level to the high level. Thus, the capacitor C1 is charged, and the signal level of oscillation signal OSC1 is increased, while the capacitor C2 is discharged, and the signal level of the oscillation signal OSC2 is reduced. In the above-described manner, the reference clocks CK1 and CK2, each having a frequency corresponding to a time constant of the oscillator circuit 91.